Conventional I/O bus arbiters and enabling technology developments.
Conventional I/O (Input/Output) bus arbiters are required in multibus system in SOC (System-On-Chip) architectures from the simple to the complex with not only a plurality of buses but plurality of arbiters too. For example, in an advanced communications processor such as the Intel IXP435, there exists in the single chip three bus arbiters, four different buses, and two bridges, even though the SOC is a single-CPU based on the ARM architecture, though with two hardware-support accelerators or co-processors. The Intel Pentium series of computer systems, and other microcomputer-based SOC systems also worked with the same scheme.
Most arbiters need at least two signals; the REQ-GNT (Request-Grant) pair for the bus request signal from a device, and the corresponding bus grant signal from the arbiter. This is in addition to the CPU (processor) DMA (direct memory access), INT (interrupt), and BUSREQ-BUSGNT (bus request-bus grant; a bus control signal pair). This means implementing a simple arbiter requires a thorough understanding and familiarity with a particular system. Often times the DMA is the most complex device in a PC system.
Conventional arbiters assume a minimal knowledge of the sources of I/O device requirements, in many cases zero knowledge, thus the need for complex hardware schemes such as an algorithm for prioritizing, time stamp for aging, and other dubious schemes when many can be made simple by having a fore-knowledge of the device transfer capability. These schemes now need some modifications in view of current model of processing which is packet oriented such as is required in broadband devices.
An example of how an I/O arbiter was implemented is to see how one popular arbiter chip was used in a typical system. The Intel 8289 was among a pioneering arbiter chip which was designed to work with the Intel 8288 bus controller and the Intel 8086 CPU, which is the forebear of all Intel-based Pentium computers. It is part of the Intel MCS-86 family of support chips which came out after the introduction of the Intel 8086 CPU in 1978. The 8289 also allows multi-arbiter chips thus allowing more chaos, when not only devices need bus arbitration but arbiters too need arbitration!
Somebody has already thought along this line of questioning the philosophy of complex arbitration schemes. U.S. Pat. No. 7,096,293B2 granted Aug. 22, 2006 for Samsung Electronics described an arbitration scheme relying heavily on one main CPU signal, ie., the INT (interrupt) signal. But this too required use of the traditional REQ-GNT signal pair for arbitration, which the patent also included the PCI bus.
In another field of development, U.S. Pat. No. 5,185,694 granted Feb. 9, 1993 for Motorola Inc., described one new instruction, the block MOVE which is a native CPU instruction that can perform burst-transfer of data under programmer control. Though the invention described burst-transfer between memory-memory, the idea can be applied to I/O as well.
Now the burst transfer or synchronous data transfer is a requirement for system throughput such that after the 1993 patent, we saw the burst-transfer as the fundamental operation of the PCI bus specification which Intel created in 1994. It is also the same concept used in the popular SDRAM which saw use in microcomputers from that year and was the mainstay technology until replaced by DDR in 2002, and then DDR2 well into 2009.
A burst-transfer of data needs FIFOs at each side of the two transmitting and receiving ports to match differing speed capabilities. These developments paved the way for the next improvement in I/O arbiter technology which is the subject of this invention.